3GL   4GL   5GL  

86
Disassembly Visual C++

, , . CPU x86 (, , , EDX, ESI, EDI, ESP ), (CS, DS, ES, SS, FS GS), () EIP (EFLAGS). , , , . , . 6.1, 32-. , 32- . , , FS, (TIB), . , , . .

6.1.

32-

16-

( 0-7)

( 8-1 5)

AL

BL

CL

EDX

DX

DL

DH

32 64-

ESI

SI

EDI

DI

ESP

SP

. , ,

EBP

/.

EFLAGS . EFLAGS , . , ZF (Zero Flag ) 1, (0). 4 CPU (single-step mode), TF (Trap Rag ) EFLAGS. . 6.1 Registers Visual C++. Registers EFLAGS EFL. , Registers . Registers Floating-Point Registers .

. 6.2 , Registers. , Visual C++ , , Visual C++, Intel, Intel .

. 6.1. Registers Visual C++

Registers : EFL ( , ). . : New Text File ( Standard) . ( ) Registers , .

6.2. Registers

Registers

Intel

OV

Overflow Flag ( )

OF

1,

UP

Direction Flag ( )

DF

1, (). 0 , : ()

El

Interrupt Enable Flag ( )

IF

1, . (1)

PL

Sign Flag ( )

SF

() . 0 1

ZR

Zero Flag ( )

ZF

1, 0 ().

AC

Auxiliary Carry Flag ( )

AF

1, - (BCD)

PE

Parity Flag ' ( )

PF

1, () , 1

CY

Carry Flag ( )

CF

1, () . 1

Registers . ( ) .

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, , Encapsulation - .In - + Capsula - , - - . , .




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